View STDH90_1318872.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 1 introduction
table of contents 1.1 library description............................................................................................... 1-1 1.2 features............................................................................................................... 1-2 1.3 cae support........................................................................................................ 1-3 1.4 product family..................................................................................................... 1-4 1.4.1 internal macrocells ................................................................................... 1-4 1.4.2 compiled macrocells................................................................................ 1-4 1.4.3 input/output cells .................................................................................... 1-5 1.5 propagation delays ............................................................................................. 1-6 1.6 delay model......................................................................................................... 1-7 1.7 testability design methodology ........................................................................... 1-8 1.8 maximum fanouts ............................................................................................... 1-9 1.9 product line-up................................................................................................... 1-10 1.10 packages capability by lead count.................................................................. 1-11 1.11 external design interface considerations.......................................................... 1-12 1.12 power dissipation .............................................................................................. 1-13 1.13 vdd/vss rules and guidelines........................................................................ 1-14 1.14 crystal oscillator considerations....................................................................... 1-19
introduction 1.1 library description sec asic 1-3 STDH90/mdl90 1.1 library description sec asic offers STDH90/mdl90 as 0.35 m m cmos standard cell libraries based on a completely new blended process. secs world-leading dram process is merged with a sophisticated 0.35 m m cell-based logic process providing up to 4 layers of interconnect metal with various i/o padCpitch options. STDH90 and mdl90 use the same process. STDH90 can support up to three million gate count of logic providing 90% of usable gates with four layer metal. STDH90 is 40% faster than 0.5 m m second generation library std85. logic density is 2.5 times greater than that of std85. mdl90 consists of STDH90 and on-chip drams. mdl90 adds up to 24mbit of on-chip dram to the three million logic gates that STDH90 provides, truly delivering a system-on-a-chip solution. a fully con?gurable memory compiler is available and datapath elements with up to 64 bit bus width are supported. STDH90 i/o family features dual gate oxide process to support mixed-voltage designs without reducing reliability. these mixed-voltage designs interfaces between 5-volt and 3.3 volts. to better support a system-on-a-chip design style, various core cells are available including processor cores like arm7tdmi, 80c51 and oak. the list of analog core cells includes adc, dac, codec and pll. the STDH90/mdl90 design kit supports synopsys design compiler, vss, verilog-xl, powerview, mentor, motive, sunrise and ikos. sec design methodology offers a comprehensive timing solution including static timing analysis, ?oorplanning, rc extraction and delay calculation with very deep-submicron solutions from leading eda vendors. for the latest status and details, please refer to the design kit release notes.
1.2 features introduction STDH90/mdl90 1-4 sec asic 1.2 features q 3.3 volt standard cell library including process cores, analog cores and drams. q 0.35 m m quad layer metal hcmos technology C uni?ed process for dram, logic and analog q high basic cell usages C up to 3 million gates C maximum usage: 90% for quad layer metal q high speed C typical 2-input nand gate delay: 150ps (2 f/o + 2 wire load) q fully con?gurable static rams and roms C up to 512k-bit diffusion rom available C up to 128k-bit single-port static ram available C up to 64k-bit dual-port static ram q con?gurable datapath elements available C 4-64 bit bus width C adder, alu, barrel shifter, carry-select adder, multiplier, multi-port register ?le q operating temperature (t a ) C commercial range: 0?c to +70?c C industrial range: C40?c to +85?c q selectable output current drive capability C 2/4/8/12/16/24ma available for 5v q processor core integration capability including arm7tdmi, 80c51, oak and others q analog core integration capability including adc, dac, codec, pll and others q various package options q fully integrated cad software support C synopsys, vss, verilog-xl, powerview, mentor, motive and ikos q cell set optimized for synthesis
introduction 1.3 cae support sec asic 1-5 STDH90/mdl90 1.3 cae support STDH90/mdl90 supports popular design platforms and environments such as verilog, viewlogic, mentor, ikos and synopsys for front-end logic design capture, synthesis, and simulation, and avanti for back-end placement and routing. for a high simulation accuracy, STDH90/mdl90 uses a proprietary delay calculator. cell delay calculations are based on a matrix of delay parameters for each macrocell, and signal interconnection delay is based on the rc tree analysis.
introduction 1.4 product family sec asic 1-6 STDH90/mdl90 1.4 product family STDH90/mdl90 library include the following design elements: n internal macrocells n compiled macrocells n input/output cells n jtag boundary scans. 1.4.1 internal macrocells macrocells are the lowest level of logic functions such as nand, nor and ?ip-?op used for logic designs. there are about 430 different types of internal macrocells. they usually come in three levels of drive strength (1x, 2x and 4x). these macrocells have many levels of representationslogic symbol, logic model, timing model, transistor schematic, hspice netlist, physical layout, and placement and routing model. 1.4.2 compiled macrocells compiled macrocells of STDH90/mdl90 consist of compiled memory and compiled datapath macrocells. compiled memory macrocells include three single-port rams (synchronous, asynchronous and alternative), three dual-port rams (synchronous, asynchronous and alternative) and two roms (synchronous diffusion programmable and via programmable). synchronous memories have a fully synchronous operation for clock. asynchronous memories have a synchronous operation for write enable in write mode and have an asynchronous operation for address in read mode. those compiled memories have an automatic power-down mode that signi?cantly reduces power consumption for read and write operations. this power-down mode ensures that memory consumes power for the minimum amount of time needed for a read or write operation. some of memories support dual bank option to double the maximum capacity. also, flexible memory apsect ratio is provided. now, a softmacro based memory bist (built-in self test) capability is available. several memory macrocells of the same type or the different type in a circuit can be tested by single bist circuit. compiled datapath macrocells include adder, alu, barrel shifter, carry select adder, multiplier and multi-port register ?le. adder supports both addition and subtraction and adopts a group-bypass carry propagation scheme to improve performance. alu supports 9 arithmetic operations and 15 logical operations. carry select adder is much faster than adder and adopts a double-carry propagation scheme to improve performance. multiplier supports pipe-lined scheme to improve performance and also accumulation scheme. multi-port register ?le allows 1-to-2 write and 1-to-4 read ports and each port is fully independent. in write mode, this register ?le operates synchronously for clock. in read mode, it operates asynchronously for address. we provide two kinds of engineering design services. one is to support additional compiled datapath macrocells such as comparators, detectors, incrementers and decrementers, multiplexers, and so on. the other is to support hardwired datapath module design.
1.4 product family introduction STDH90/mdl90 1-7 sec asic 1.4.3 input/output cells there are about four hundred different i/o buffers. each i/o cell is implemented solely on the basic i/o cell architecture which forms the periphery of a chip. a test logic is provided to enable the ef?cient parametric (threshold voltage) testing on input buffers including cmos and ttl level converters, schmitt trigger input buffers, clock drivers and oscillator buffers. pull-up and pull-down resistors are optional features. three basic types of output buffers (non-inverting, tri-state and open drain) are available in a range of driving capabilities from 2ma to 24ma for 5 v drive . one or two levels of slew rate controls are provided for each buffer type (except 2ma buffers) to reduce output power/ground noise and signal ringing, especially in simultaneous switching outputs. bi-directional buffers are combinations of input buffers and output buffers (tri-state or open drain) in a single unit. the i/o structure has been fully characterized for esd protection and latch-up resistance. for users convenience, STDH90/mdl90 library provides 50 k w pull-down and pull-up resistances respectively. 1.4.3.1 i/o cell drives options to provide designers with the greater ?exibility, each i/o buffer can be selected among various current levels (e.g., 2ma, 4ma, ..., 24ma). the choice of current-level for i/o buffers affects their propagation delay and current noise. the slew rate control helps decrease the system noise and output signal overshoot/undershoot caused by the switching of output buffers. the output edge rate can be slowed down by selecting the high slew rate control cells. STDH90/mdl90 provides three different sets of output slew rate controls. only one i/o slot is required for any slew rate control options.
introduction 1.5 propagation delays sec asic 1-8 STDH90/mdl90 1.5 propagation delays refer to std90/mdl90.
introduction 1.6 delay model sec asic 1-9 STDH90/mdl90 1.6 delay model refer to std90/mdl90.
introduction 1.7 testability design methodology sec asic 1-10 STDH90/mdl90 1.7 testability design methodology refer to std90/mdl90.
introduction 1.8 maximum fanouts sec asic 1-11 STDH90/mdl90 1.8 maximum fanouts 1.8.1 internal macrocells refer to std90/mdl90. 1.8.2 clock drivers std90 max fanout for clock drivers ? clock trunk width = 8 um ? clock trunk length = 5,000 um ? capacitance per fanout = 0.007838 pf (= input capacitance for ck pin of fd1) ? standard load(sl) = 0.011 pf (= input capacitance for iv) ? net length = 200 um per fanout ? max output transition time = 3.0 ns ? frequency 120 mhz table 1-1. maximum fanout of clock drivers for a design with an operating frequency higher than 120 mhz, sec strongly recommends using clock tree synthesis. 1.8.3 i/o cells the maximum fanouts for i/o cells are as follows. table1-2. maximum fanouts of i/o cells(when input tr/tf = 1.6ns) cell type # of fanout # of sl ck2x 522 379 ck3x 703 511 ck4x 788 572 cell class output pin maximum fanouts cell class output pin maximum fanouts phic y 263 phili y 263 phicd50 y 264 philid50 y 263 phicu50 y 264 philiu50 y 263 phil y 262 phisi y 263 phild50 y 264 phisid50 y 263 philu50 y 264 phisiu50 y 263 phis y 263 phitata y 264 phisd50 y 262 phitu50ata y 264 phisu50 y 263 phiti y 263 phit y 264 phitid50 y 263 phitd50 y 264 phitiu50 y 264 phitu50 y 263 phsosclf y 933 phitu5 y 263 phsoscmf y 1138 phitu50c y 263 phsoschf y 1860
introduction 1.9 product line-up sec asic 1-12 STDH90/mdl90 1.9 product line-up refer to std90/mdl90.
introduction 1.10 package capability by lead count. sec asic 1-13 STDH90/mdl90 1.10 package capability by lead count. refer to std90/mdl90.
introduction 1.11 external design interface considerations sec asic 1-14 STDH90/mdl90 1.11 external design interface considerations refer to std90/mdl90.
introduction 1.12 power dissipation sec asic 1-15 STDH90/mdl90 1.12 power dissipation refer to std90/mdl90.
introduction 1.13 vdd/vss rules and guidelines sec asic 1-16 STDH90/mdl90 1.13 vdd/vss rules and guidelines there are three types of v dd and v ss in STDH90/mdl90, providing power with internal and i/o pad area. ? core logic C vdd3i, vssi ? pre-drive (i/o area) C vdd5p, vssp ? output-drive (i/o area) C vdd5o, vsso the number of v dd and v ss pads required for a speci?c design depends on the following factors: ? number of input and output buffers ? number of simultaneous switching outputs ? number of used gates and simultaneous switching gates ? operating frequency of the design. 1.13.1 basic placement guidelines the purpose of these guidelines is to minimize ir drop and noise for reliable device operation. ? core logic and pre-driver vdd/vss pads should be evenly distributed on all sides of the chip. ? if you have core block demanding high power(compiled memory,analog) , extra power pads should be placed on that side. ? power pads for sso group should be evenly distributed in the sso group. ? do not place the high drive output or bi-directional buffer next to a sso group. ? opposite type power pads(vdd/vss) should be placed as close as possible. same type power pads(vdd/vdd,vss/vss) should be separated. these two placement scheme will reduce the mutual inductance of lead of power pads. 1.13.2 core logic v dd /v ss bus and vddi/vssi pad allocation guidelines the purpose of these guidelines is to ensure that minimum number of core logic power pad pairs requirement based on electro-migration current limit. the number of v dd /v ss pads required for a speci?c design is the function of the operating frequency of a chip, i.e., designs operating at high frequency should use more v dd /v ss pads. ?v dd bus width and pad requirements are equal to those of v ss .
1.13 vdd/vss rules and guidelines introduction STDH90/mdl90 1-17 sec asic ?v dd /v ss buses and pads should be distributed evenly in the core and on all sides of the chip. ? the total number of core logic v dd i pads required is equal to that of vssi pads the number of vssi/vddi pad pairs required for a design can be calculated from the following expression: the number of vddi/vssi pad pairs = || (g x s x f x gc eq_current ) + { ? (p_i x f_i)} / i em || round-up in the above formula, g = the core ( excluding hard macro blocks) size in gate counts s = % of simultaneous switching gates (default = 0.2) f = switching frequency (mhz) gc eq_current = equivalent power(current) per gate(0.101uw/mhz/v) p_i = characterized power (current) for the i-th hard macro block(ma/mhz) f_i = switching frequency for the i-th hard macro block(mhz) l em = current limit per vdd/vss pad pairs based on electromigration rule. (100ma) for reliable device operation and minimum ir voltage drop, minimum number of vssi/vddi pad pairs is 4. extra power may be needed for the demanding high power macro blocks (sram,analog block,and so on) 1.13.3 input buffer v dd /v ss pad vddp/vssp allocation guidelines these guidelines ensure that an adequate input threshold voltage margin is maintained during a switching. the number of vssp/vddp pad pairs required for a design can be calculated from the following expression: the number of vddp/vssp pad pairs = || ieq_p / i em ||round-up in the above formula, ieq_p = ? (average current of input buffers and output pre-drivers at maximum operating frequency) l em = current limit per vdd/vss pad pairs based on electro-migration rule. (100 ma)
introduction 1.13 vdd/vss rules and guidelines sec asic 1-18 STDH90/mdl90 table 1-3. leq_p(at f=100mhz) value of each input buffer and output pre-driver. table 1-3(a). leq_p(at f=100mhz) value of each type of input buffer table 1-3(b). leq_p(at f=100mhz) value of each type of output pre-driver if buffer type is bi-directional, then you should combine the proper input buffer and output pre-driver leq_p value. for reliable device operation and minimum ir voltage drop, minimum number of vssp/vddp pad pairs is 4. in order to minimize number of power pads, you may use combined power pad. you can get the combined power pad pairs vddip/vssip from the following formula. the number of vddip/vssip pad pairs = || (g x s x f x gc eq_current ) + { ? (p_i x f_i)} / i em + ieq_p / i em || round-up for reliable device operation and minimum ir voltage drop, minimum number of vssip/vddip pad pairs is 4. 1.13.4 output buffer v dd /v ss pad vddo/vsso allocation guidelines sso(simultaneous switching output) current induced in power and ground inductance can cause system failure because of voltage ?uctuations. in case of output driver power pad calculation, we consider the sso noise as well as current limit based on electro-migration. we may de?ne sso as outputs are considered to be simultaneous in 1ns window such as bus type buffers. the number of vddo/vsso pads required for a device can be calculated from the following expressions. ? the number of power pads for each sso group from the following formula. nvddo each_sso = (number_of_sso x l lead ) / (d sso_mode x nb vdd ) nvsso each_sso = (number_of_sso x l lead ) / (d sso_mode x nb vss ) in the above formula, input buffer type cmos cmos schmitt ttl ttl schmitt ieq_p(ma) 0.37 0.45 0.30 0.53 output slew-rate type normal medium high ieq_p(ma) 1.0 1.2 1.8
introduction 1.13 vdd/vss rules and guidelines sec asic 1-19 STDH90/mdl90 nvddo each_sso = the number of vddo pads required for each sso group nvsso each_sso = the number of vsso pads required for each sso group nb vdd = the number of buffers per vdd power pad with 1nh lead inductance nb vss = the number of buffers per vss ground pad with 1nh lead inductance l lead = lead frame inductance of package (refer to 1.10 package capability by lead count) d sso_mode =d l_mode x d p_mode x d v_mode x d t_mode x d c_mode d l_mode : lead inductance derating factor d p_mode : process derating factor d v_mode : voltage derating factor d t_mode : temperature derating factor d c_mode : c load derating factor (mode is either vdd or vss. refer to table 1.4) table 1-4. derating equation item mode equation range package lead d l_vdd 0.0052 * lpg + 0.9794 -0.0052 * lpg + 1.0825 3nh lpg 10nh 10nh < lpg 15nh d l_vss -0.0094 * lpg + 1.0377 0.0377 * lpg + 0.5660 3nh lpg 10nh 10nh < lpg 15nh process d p_vdd 1 best 1.1134 typical 1.2887 worst d p_vss 1 best 1.3208 typical 1.5094 worst voltage d v_vdd -0.2222 * voltage + 2.1556 4.5 voltage 5.0 -0.1778 * voltage + 2.9333 5.0 < voltage 5.5 d v_vdd -0.2500 * voltage + 2.2812 4.5 voltage 5.0 -0.1250 * voltage + 1.6562 5.0 < voltage 5.5 temp. d t_vdd 0.0008 * temp + 1.0000 -40 temp 25 0.0006 * temp + 1.0066 25 < temp 125 d t_vdd 0.0045 * temp + 1.0000 -40 temp 25 0.0034 * temp + 1.0274 25 < temp 125 cload d c_vdd 0.0155 * cload + 0.5361 10pf cload 30pf 0.0180 * cload + 0.4588 30pf < cload 100pf d c_vdd 0.0255 * cload + 0.2358 10pf cload 30pf 0.0142 * cload + 0.5755 30pf < cload 100pf
introduction 1.13 vdd/vss rules and guidelines sec asic 1-20 STDH90/mdl90 ? the number of power pads for total sso groups from the following formula. nvddo sso = ? nvddo each_sso nvsso sso = ? nvsso each_sso in the above formula, nvddo sso = the number of vddo pads required for total sso groups nvsso sso = the number of vsso pads required for total sso groups ? the number of power pads for non-sso group from the following formula. n nsvddo = i eq_o / i em n nsvsso = i eq_o / i em in the above formula, i eq_o = ? (c load x v x f x p) non-sso c load : output load capacitance v : operating voltage f : operating frequency p : i/o switching percent(marginal=0.5) i em : current density based on electro-migration rule(100ma) ? the total number of power pads for vddo from the following formula. || ? (number_of_sso x l lead ) / (d sso_mode x nb vdd ) + i eq_o / i em || round-up ? the total number of power pads for vsso from the following formula. || ? (number_of_sso x l lead ) / (d sso_mode x nb vss )+ i eq_o / i em ) || round-up if you use open-drain type buffers, you can consider only vsso power pads because they have only current sink. table 1-5. nbvdd/nbvss parameter (condition : process=best , voltage=5.25v , temp=0 ? c , cload=30pf) buffer type normal medium high nbvdd nbvss nbvdd nbvss nbvdd nbvss b2 170 116 b4 84 55 89 58 b8 39 28 40 29 b12 28 20 30 21 31 22 b16 23 16 24 17 26 18 b24 19 13 20 14 22 15
1.14 crystal oscillator consideration introduction STDH90/mdl90 1-21 sec asic 1.14 crystal oscillator consideration refer to std90/mdl90.

▲Up To Search▲

Price & Availability of STDH90

	To Download STDH90 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .